Picture 1 of 2
Stock photo
Picture 1 of 2
Stock photo
SystemVerilog for Design Second Edition : A Guide to Using SystemVerilog for Hardware Design and Modeling by Simon Davidmann, Peter Flake and Stuart Sutherland (2010, Trade Paperback)
BooksRun (221895)
99.5% positive feedback
Price:
US $87.85
ApproximatelyRM 368.69
+ $20.83 shipping
Returns:
30 days return. Buyer pays for return shipping. If you use an eBay shipping label, it will be deducted from your refund amount.
Condition:
Oops! Looks like we're having trouble connecting to our server.
Refresh your browser window to try again.
About this product
Product Identifiers
PublisherSpringer
ISBN-101441941258
ISBN-139781441941251
eBay Product ID (ePID)121315863
Product Key Features
Number of PagesXxx, 418 Pages
LanguageEnglish
Publication NameSystemVerilog for Design Second Edition : A Guide to Using SystemVerilog for Hardware Design and Modeling
Publication Year2010
SubjectHardware / General, Computer Simulation, Cad-Cam, Electronics / Circuits / General, Electronics / Digital, Logic Design
TypeTextbook
Subject AreaComputers, Technology & Engineering
AuthorSimon Davidmann, Peter Flake, Stuart Sutherland
FormatTrade Paperback
Dimensions
Item Weight24.1 Oz
Item Length9.3 in
Item Width6.1 in
Additional Product Features
Edition Number2
Intended AudienceScholarly & Professional
Number of Volumes1 vol.
IllustratedYes
Table Of Contentto SystemVerilog.- SystemVerilog Declaration Spaces.- SystemVerilog Literal Values and Built-in Data Types.- SystemVerilog User-Defined and Enumerated Types.- SystemVerilog Arrays, Structures and Unions.- SystemVerilog Procedural Blocks, Tasks and Functions.- SystemVerilog Procedural Statements.- Modeling Finite State Machines with SystemVerilog.- SystemVerilog Design Hierarchy.- SystemVerilog Interfaces.- A Complete Design Modeled with SystemVerilog.- Behavioral and Transaction Level Modeling.
SynopsisIn its updated second edition, this book has been extensively revised on a chapter by chapter basis to include the many text and example updates needed to reflect changes adopted between the first edition of the book and the finalization of the new standard. The book accurately reflects the syntax and semantic changes to the SystemVerilog language, making it an essential reference for systems professionals who need the latest version information. In addition, the second edition features a new chapter that explains the SystemVerilog "packages", a new appendix that summarizes the synthesis guidelines presented throughout the book, and all of the code examples have been updated to the final syntax and rerun using the latest version of the Synopsys, Mentor, and Cadance tools., SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL-based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs to efficiently and effectively verify these large designs. The first edition of this book addressed the first aspect of the SystemVerilog extensions to Verilog. Important modeling features were presented, such as two-state data types, enumerated types, user-degined types, structures, unions, and interfaces. Emphasis was placed on the proper usage of these enhancements for simulation and synthesis. SystemVerilog for Design, Second Edition has been extensively revised on a chapter by chapter basis to include the many text and example updates needed to reflect changes that were made between the first edition of this book was written and the finalization of the new standard. It is important that the book reflect these syntax and semantic changes to the SystemVerilog language. In addition, the second edition features a new chapter that explanis the SystemVerilog "packages", a new appendix that summarizes the synthesis guidelines presented throughout the book, and all of the code examples have been updated to the final syntax and rerun using the latest version of the Synopsys, Mentor, and Cadance tools., In its updated second edition, this book has been rewritten chapter-by-chapter to accurately reflect the syntax and semantic changes to the SystemVerilog language standard, making it an essential reference for systems professionals who need the latest version information
LC Classification NumberTK7867-7867.5
Be the first to write a review
