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Verilog HDL : A Guide to Digital Design and Synthesie Bk/CD-ROM H
Free US Delivery | ISBN:0134516753
US $6.72
ApproximatelyRM 28.50
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“Used book that is in clean, average condition without any missing pages. 100% Money-Back Guarantee.”
Good
A book that has been read but is in good condition. Very minimal damage to the cover including scuff marks, but no holes or tears. The dust jacket for hard covers may not be included. Binding has minimal wear. The majority of pages are undamaged with minimal creasing or tearing, minimal pencil underlining of text, no highlighting of text, no writing in margins. No missing pages.
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Located in: Reno, Nevada, United States
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Estimated between Fri, 18 Jul and Mon, 21 Jul to 94104
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eBay item number:376236435568
Item specifics
- Condition
- Good
- Seller Notes
- “Used book that is in clean, average condition without any missing pages. 100% Money-Back Guarantee.”
- Book Title
- Verilog HDL : A Guide to Digital Design and Synthesie Bk/CD-ROM H
- ISBN
- 9780134516752
About this product
Product Identifiers
Publisher
Prentice Hall PTR
ISBN-10
0134516753
ISBN-13
9780134516752
eBay Product ID (ePID)
43013
Product Key Features
Number of Pages
448 Pages
Publication Name
Verilog Hdl : a Guide to Digital Design and Synthesie (BK/CD-ROM)
Language
English
Subject
Software Development & Engineering / Systems Analysis & Design, Logic Design
Publication Year
1996
Type
Textbook
Subject Area
Computers
Format
Hardcover
Dimensions
Item Height
0.9 in
Item Weight
30.4 Oz
Item Length
9.6 in
Item Width
7.2 in
Additional Product Features
Intended Audience
College Audience
LCCN
96-173039
Dewey Edition
20
Illustrated
Yes
Dewey Decimal
621.3/92
Table Of Content
PART I. BASIC VERILOG TOPICS. 1. Overview of Digital Design with Verilog HDL. Evolution of Computer Aided Digital Design. Emergence of HDLs. Typical Design Flow. Importance of HDLs. Popularity of Verilog HDL. Trends in HDLs. 2. Hierarchical Modeling Concepts. Design Methodologies. 4-bit Ripple Carry Counter. Modules. Instances. Components of a Simulation. Example. Design Block. Stimulus Block. Summary. Exercises. 3. Basic Concepts. Lexical Conventions. Whitespace. Comments. Operators. Number Specification. Sized numbers. Unsized numbers. X or Z values. Negative numbers. Underscore characters and question marks. Strings. Identifiers and Keywords. Escaped Identifiers. Data Types. Value Set. Nets. Registers. Vectors. Integer , Real, and Time Register Data Types. Integer. Real Time. Arrays. Memories. Parameters. Strings. System Tasks and Compiler Directives. System Tasks. Displaying information. Monitoring information. Stopping and finishing in a simulation. Compiler Directives. 'define. 'include. Summary. Exercises. 4. Modules and Ports. Modules. Ports. List of Ports. Port Declaration. Port Connection Rules. Inputs. Outputs. Inouts. Width matching. Unconnected ports. Example of illegal port connection. Connecting Ports to External Signals. Connecting by ordered list. Connecting ports by name. Hierarchical Names. Summary. Exercises. 5. Gate-Level Modeling. Gate Types. And/Or Gates. Buf/Not Gates. Bufif/notif. Examples. Gate-level multiplexer. 4-bit full adder. Gate Delays. Rise, Fall, and Turn-off Delays. Rise delay. Fall delay. Turn-off delay. Min/Typ/Max Values. Min value. Typ val. Max value. Delay Example. Summary. Exercises. 6. Dataflow Modeling. Continuous Assignments. Implicit Continuous Assignment. Delays. Regular Assignment Delay. Implicit Continuous Assignment Delay. Net Declaration Delay. Expressions, Operators, and Operands. Expressions. Operands. Operators. Operator Types. Arithmetic Operators. Binary operators. Unary operators. Logical Operators. Relational Operators. Equality Operators. Bitwise Operators. Reduction Operators. Shift Operators. Concatenation Operator. Replication Operator. Conditional Operator. Operator Precedence. Examples. 4-to-1 Multiplexer. Method 1: logic equation. Method 2: conditional operator. 4-bit Full Adder. Method 1: dataflow operators. Method 2: full adder with carry lookahead. Ripple Counter. Summary. Exercises. 7. Behavioral Modeling. Structured Procedures. Initial Statement. Always Statement. Procedural Assignments. Blocking assignments. Nonblocking Assignments. Application of nonblocking assignments. Timing Controls. Delay-Based Timing Control. Regular delay control. Intra-assignment delay control. Zero delay control. Event-Based Timing Control. Regular event control. Named event control. Event OR control. Level-Sensitive Timing Control. Conditional Statements. Multiway Branching. Case Statement. Casex, casez Keywords. Loops. While Loop. For Loop. Repeat Loop. Forever loop. Sequential and Parallel Blocks. Block Types. Sequential blocks. Parallel blocks. Special Features of Blocks. Nested blocks. Named blocks. Disabling named blocks. Examples. 4-to-1 Multiplexer. 4-bit Counter. Traffic Signal Controller. Specification. Stimulus. Summary. Exercises. 8. Tasks and Functions. Differences Between Tasks and Functions. Tasks. Task Declaration and Invocation. Task Examples. Use of Input and Output Arguments. Asymmetric Sequence Generator. Functions. Function Declaration and Invocation. Function Examples. Parity calculation. Left/right shifter. Summary. Exercises. 9. Useful Modeling Techniques. Procedural Continuous Assignments. Assign and deassign. Force and release. Force and release on registers. Force and release on nets. Overriding Parameters. Defparam Statement. Module_
Synopsis
For Verilog HDL digital IC and system design professionals. Verilog HDL is a language for digital design, just as C is a language for programming. This complete Verilog HDL reference progresses from the basic Verilog concepts to the most advanced concepts in digital design.
LC Classification Number
TK7885.7.P35 1996
Item description from the seller
Seller feedback (429,069)
- b***l (2630)- Feedback left by buyer.Past monthVerified purchaseNot what I expected from the description. Yes, it is used and from a library. No I did not expect the pages to stick together. No, it is not pencil/pen marked up, just some stains which may account for the pages that were sticking together along the edges. At best, in my opinion, it is at the "acceptable" stage.
- o***d (1953)- Feedback left by buyer.Past monthVerified purchaseThanks 🙂
- a***a (24)- Feedback left by buyer.Past monthVerified purchaseGreat seller!
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Seller feedback (429,069)
- b***l (2630)- Feedback left by buyer.Past monthVerified purchaseNot what I expected from the description. Yes, it is used and from a library. No I did not expect the pages to stick together. No, it is not pencil/pen marked up, just some stains which may account for the pages that were sticking together along the edges. At best, in my opinion, it is at the "acceptable" stage.
- o***d (1953)- Feedback left by buyer.Past monthVerified purchaseThanks 🙂
- a***a (24)- Feedback left by buyer.Past monthVerified purchaseGreat seller!